1. Field of the Invention
The present invention relates generally to branch prediction in a microprocessor system and, more particularly, to a method and apparatus for predicting branches to be taken in a microprocessor system capable of executing a plurality of instruction sets.
2. Description of the Related Art
A microprocessor's performance is directly related to the amount of time it is busy executing instructions. It achieves maximum performance if it never sits idle waiting on fetches from memory or I/O. The microprocessor has an efficiency circuit called the prefetch unit, which has the responsibility of keeping the execution unit as busy as possible by providing a constant flow of instructions. The prefetch unit is responsible for keeping enough instructions on hand so the microprocessor does not stop its execution flow to fetch an instruction from memory. This look-ahead feature can significantly increase performance, because much of the time, the next instruction is already waiting at the first stage of the microprocessor's execution pipeline. If instructions are sequentially stored, prefetching almost guarantees that the next instruction will always be ready.
However, instruction sequences are not always stored in memory one after another. Software contains branches or jumps in instruction flow that cause the microprocessor to jump around to different sections of code depending on the task being executed. The prefetch unit can keep track of the current instruction flow, but it doesn't know the future.
Performance of the microprocessor is further enhanced by a second efficiency circuit called the branch prediction unit, which works in concert with the prefetch unit. The branch prediction unit, as its name suggests, attempts to predict whether a branch will be taken. As long as the branch prediction unit is right, the prefetch unit speeds along retrieving the next instruction to be executed. In Intel's Pentium microprocessor, the branch prediction unit is typically right about 90% of the time, resulting in an overall performance increase of about 25%. A wrong prediction is corrected in about 3 or 4 clock cycles. That is, once the branch prediction unit determines that its prediction was wrong, it flushes the pipeline of instructions, and passes the address for the correct next instruction to the prefetch unit. The prefetch unit again speeds along fetching the next series of instructions to be executed.
The method used to accurately predict branches is highly dependent upon the architecture of the instruction set being executed. An efficient method of predicting branches in a RISC microprocessor may not be efficient, or even applicable, to a CISC microprocessor. Accordingly, in a microprocessor intended to execute two or more instruction sets by translating the instructions into a common instruction set, branch prediction becomes more complex.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above by providing a novel and nonobvious method and apparatus for predicting branches in a multiple instruction-set architecture microprocessor.